12MB of L2 cache per processor (each pair of cores shares 6MB)
128-bit SSE4 SIMD engine
64-bit data paths and registers
Energy efficiency optimization
1600MHz, 64-bit dual independent frontside buses
12MB of L2 cache per processor (each pair of cores shares 6MB)
128-bit SSE4 SIMD engine
64-bit data paths and registers
Energy efficiency optimization
1600MHz, 64-bit dual independent frontside buses
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Since we're talkin about processor cores, how about like 70 cores, and like 40 Terabytes? :-)
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